The present invention generally relates to genetic algorithms and evolvable hardware, and more particularly to a method for evolving configuration bitstreams for programmable logic devices.
Many conventional design methodologies are based on a structured design approach. That is, high-level requirements are partitioned, perhaps hierarchically, into lower-level requirements. Teams of engineers are assigned to create designs and sub-designs that meet the requirements at the different levels. The structured design methodology is advantageous because it supports building on past experiences in addressing similar types of requirements, thereby promoting development of an effective design in an efficient manner. However, a drawback to traditional design methods is that the same experiences that promote quickly satisfying a requirement may blind engineers to alternative, and perhaps better, solutions.
Work is presently underway to fundamentally change the way in which designs are created. The new methodology uses principles of natural selection from the biological world to create electronic hardware designs. The process is often characterised as xe2x80x9cevolvable hardwarexe2x80x9d or using genetic algorithms to create hardware designs. In an example process of evolving a design, a population of designs is first randomly created, tested, and scored based on the suitability to meet the design requirements. Then based on natural selection principles, certain ones of the designs in the population are selected to xe2x80x9creproduce,xe2x80x9d that is, used to create new designs for the population. The process of testing, scoring, and reproducing is then repeated until a suitable design has evolved.
The hardware used in evolving designs is typically some type of programmable logic device. SRAM FPGAs are suitable because they can be programmed, tested, and reprogrammed many times in evolving a design. The XC6200 FPGA from XILINX has been often used for the additional reason that the architecture does not allow contention in the device, no matter what the bitstream is.
A problem often encountered with evolving designs for other SRAM FPGA architectures is that the objective designs are usually intended to be digital solutions for digital devices (e.g., a bitstream for an FPGA), but an evolved design can cause a digital device to exhibit unintended asynchronous behavior and even contain contentions for resources capable of destroying the device. For example, widely used commercial parts, such as the XC4000EX/XL and Virtex FPGAs from XILNX, can be damaged if multiple signals are allowed to drive the same wire. Thus, such parts have been avoided for evolving hardware.
At present, testing the evolving circuits is very time consuming. Many hours are spent reading and writing configuration bitstreams and testing the fitness of the bitstreams. Some implementations use dedicated input/output ports for probing the evolving designs. However, dedicating input/output ports to testing limits the portability of the design. Further, setting up the hardware for a test procedure is expensive. A test system board must include several IC devices for performing the tests, and these IC devices may not be configurable. If these non-configurable IC devices do not perform properly with an evolved design, the tests may not be valid or useful, and the hardware may have to be changed.
Today""s evolved circuits tend to be suitable for implementation on specific devices. Irregularities in device fabrication, operating temperature, operating voltage, and other environmental factors can affect a circuit""s performance, and thus, its fitness. Therefore, an evolved circuit is rarely suitable for implementation on a variety of devices.
A method that address the aforementioned problems, as well as other related problems, is therefore desirable.
The purpose of including test circuits in the FPGA design is to drive test data to the evolved design and collect data from the design in order to evaluate the evolved circuit. The invention provides a method and apparatus for evolving configuration bitstreams having built-in test circuits. These test circuits can take test data from other devices or programs and apply the data to the evolved circuit under test.
In one embodiment, a method is provided for evolving configuration bitstreams for a programmable logic device. The method comprises providing a test circuit to be implemented on the programmable logic device. A population of configuration bitstreams is created, wherein each bitstream implements the test circuit and has a selected portion that is evolvable. The respective selected portions of the configuration bitstreams are evolved until at least one predetermined criterion is met.
In another method, a test circuit is provided to be implemented on the programmable logic device. Chromosome data structures are established having data associated with programming resources of the programmable logic device, and respective configuration bitstreams are created from data of the chromosome data structures and the test circuit. The respective configuration bitstreams that include the test circuit are evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device, and the chromosome data structures are evolved until at least one predetermined criterion is met.
In another embodiment an apparatus is provided. The apparatus comprises: means for providing a test circuit to be implemented on the programmable logic device; means for establishing chromosome data structures having data associated with programming resources of the programmable logic device; means for creating respective configuration bitstreams from data of the chromosome data structures and the test circuit; means for evaluating the respective configuration bitstreams that include the test circuit for relative suitability to meet predetermined criteria when deployed on a programmable logic device; and means for evolving data in the chromosome data structures based on the relative suitability until at least one predetermined criterion is met.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.